Design And Implementation Of High Speed Vedic Multiplier
Journal Title: International Journal of engineering Research and Applications - Year 2018, Vol 8, Issue 5
Abstract
Vedic mathematics is the ancient Indian system of mathematics. This paper proposed the design oh high speed Vedic Multiplier using the techniques of Ancient Indian Vedic Mathematics that has been modified to improve performance. Multipliers play a major role in processors and in many computational systems. The speed of these systems greatly depends on the speed of its multipliers. In order to enhance the speed of the systems the faster and efficient multipliers should be employed. Vedic Multiplier is one of the best solution which is capable of performing the quicker multiplications by eliminating the unwanted steps in the multiplication process. Vedic Multiplier deals with a total of sixteen sutras or algorithms for predominantly logical operations. In this paper it is used for designing a high speed, low power 4X4 multiplier. In the proposed design we have reduced the number of logic levels, thus reducing the logic delay. The proposed system is design using VHDL and it is implemented through Xilinx 8.1.
Authors and Affiliations
Hitansu Sekhar Sahu, Khirod Kumar Sethi, Tejesh Kumar Chaudhary, Hemant Kumar Besra, Prasanta Kumar Parida, Subha Ranjan Sahoo, Abhinash Kumar Pala
Keywords
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