Design and Implementation of Logic Gates and Adder Circuits on FPGA Using ANN
Journal Title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) - Year 2016, Vol 4, Issue 5
Abstract
In this paper, Design and hardware implementation of multiple neurons on Field Programmable (FPGA)is done sequentially. First Multiple Neurons are implemented then logic Gates and Adder circuit are implemented using Feed Forward Neural Network. FPGA has been used to reduce the neuron hardware by designing activation function inside the neuron without using lookup tables. With low precision neural network designs, FPGA's have higher speed and smaller in size for real time applications compare to VLSI.
Authors and Affiliations
Neelu Farha, Ann Louisa Paul J, Naadiya Kousar L S, Devika S
Keywords
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