Design and implementation of low power 16 bit ALU with clock gating
Journal Title: International Journal of Advanced Research in Computer Engineering & Technology(IJARCET) - Year 2013, Vol 2, Issue 6
Abstract
The ALU is one of the most frequently accessed modules in a CPU and is utilized during most instruction executions. Hence the power consumption of the ALU is a major concern.In this paper a low power 16 bit ALU is designed using VHDL. Lower power consumption is achieved by using clock gating technique and the results are compared with conventional ALU design. A carry skip adder with variable block length is used for the arithmetic unit to achieve better performance. The design is then implemented inXilinx Spartan 3E FPGA . The ALU achieves a maximum frequency of 65.19 MHzwith a dynamic power dissipation of 1.98mW when operated at 15 MHz.
Authors and Affiliations
AnkitMitra
Keywords
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- EP ID EP87762
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