Design and Implementation of UART with DFT-BIST for Data Communication
Journal Title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) - Year 2017, Vol 5, Issue 4
Abstract
The increasing growth of VLSI technology has resulted in the difficulty of testing. Design and test engineers have no choice but to accept new responsibilities that had been performed by groups of technicians in the previous years. Asynchronous serial communication is generally implemented by Universal Asynchronous Receiver Transmitter (UART), commonly used for low distance, low speed, low cost data exchange between peripherals and processor.UART allows full duplex serial communication link. It is also used in data communication and control system. The need for realizing the UART function in a single or a very few chips. The design systems without full testability are open to the increased possibility of product failures and missed market opportunities. Also, there is a need to ensure the data transfer is error proof. In This paper targets the introduction of Built-in self test (BIST) with DFT logic and Status register to UART, to overcome the above two constraints of testability and data integrity. The 8-bit UART with status register and BIST module is coded in V HDL and synthesized and simulated using Xilinx XST and modelsim version 6.3 and realized on Vertex 5 FPGA. The result shows that this model eliminates the complexity, and analysis shows the power and utilization both are minimized by the design.
Authors and Affiliations
P. Surendar, G. Gopalakrishnan
Keywords
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- EP ID EP23828
- DOI http://doi.org/10.22214/ijraset.2017.4122
- Views 247
- Downloads 7
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