Design and Verification of Adaptive Router for NOC Using Buffer Resizing Technique
Journal Title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) - Year 2016, Vol 4, Issue 7
Abstract
This paper focuses on design of adaptive router with buffer resizing technique for network on chip(NOC) by run time reconfiguration of resources and verification of design using system verilog. Complex system on chip(SOC) designs requires high bandwidth interconnects, NOC provides solution with a relative area and delay overhead. Run time usage of resources improves performance and reduces area of NOC. Functional verification ensures the quality of silicon, 60% of design time is spent on verification. To overcome this verification delay the proposed design adopts latest verification methodologies. The design is verified using a reusable test bench written in system verilog. The design of adaptive router is developed in Verilog, synthesized and simulated in Xilinx ISE Design Suite 12.4 tool. The design is verified using system verilog using Questa SIM tool.
Authors and Affiliations
Snehalata Patil, T. C Thanuja
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