Design and VLSI Implementation of 8-Bit Pipelined ADC Using Cadence 180nm Technology
Journal Title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) - Year 2015, Vol 3, Issue 9
Abstract
Analog-to-Digital converters (ADC) are key building blocks of analog and mixed signal processing that link the natural world of analog signals and the world of digital processing. Applications such as wireless communication, digital video audio have intended for price-effective data converters with signal bandwidth of tens of MHz that will achieve speed, resolution and lower power consumption. Out of available ADC’s, pipelined ADC have attractive feature of maximum conversion rate less complexity and power consumption. So it is used extensively. This work is design of an 8-bit Pipeline Analog-to-Digital Converter (ADC) which is realizing using CMOS technology. The sampling rate of the converter is about 10 MS/s, Integral NonLinearity is less than 0.9LSB and Differential Non-linearity is less than 1.02LSB with the power dissipation of less than 352.4 mW. CMOS level schematic diagram of the pipelined ADC sub-blocks have been designed utilizing Cadence Virtuoso 180nm technology at an operating voltage of 1.8 volts.
Authors and Affiliations
Indhudhara Gowda T G, Manasa A
Keywords
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