Design of 32 Bit Vedic Multiplier using Carry Look Ahead Adder
Journal Title: GRD Journal for Engineering - Year 2018, Vol 3, Issue 0
Abstract
The digital architecture is mainly used in all type of real world application architectures and thus the architecture modify based on enhancement purpose. The VISI is to optimize the any type of digital architecture. Multiplication is an important fundamental function in arithmetic logic operation. Computational performance of a DSP system is limited by its multiplication performance and since, multiplication dominates the execution time of most DSP algorithms. Multiplication is one of the basic arithmetic operations and it requires substantially more hardware resources and processing time than addition and subtraction. Vedic Mathematics is the ancient system of mathematics which has a unique technique of calculation based on 16 Sutras. Our work is to develop the 32 –bit Vedic multiplier architecture using carry look ahead adder technique.
Authors and Affiliations
Divya. P, Surya. K, Uma Narayani. R, Vidhiya. B, Sathya. G
Keywords
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