DESIGN OF 7-BIT LOW-POWER, LOW AREA A/D CONVERTER IN SUBMICRON PROCESS FOR MULTICHANNEL SYSTEMS
Journal Title: Informatyka Automatyka Pomiary w Gospodarce i Ochronie Środowiska - Year 2013, Vol 3, Issue 2
Abstract
The design of analog-to-digital converter implemented in CMOS 180 nm technology has been presented in this paper. The successive approximation architecture with charge redistribution has been chosen. Much emphasis was placed on limiting the area occupancy of the whole chip so as its power consumption, which makes the described circuit suitable for multichannel applications. The presented converter achieves 3 MS/s sampling rate with 7-bit resolution at 77 μW and occupies only 90 x 95 μm2.
Authors and Affiliations
Piotr Otfinowski, Rafał Kłeczek
Keywords
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