Design of a High Speed Architecture of MQ-Coder for JPEG2000 on FPGA

Abstract

Digital imaging is omnipresent today. In many areas, digitized images replace their analog ancestors such as photographs or X-rays. The world of multimedia makes extensive use of image transfer and storage. The volume of these files is very high and the need to develop compression algorithms to reduce the size of these files has been felt. The JPEG committee has developed a new standard in image compression that now also has the status of Standard International: JPEG 2000. The main advantage of this new standard is its adaptability. Whatever the target application, whatever resources or available bandwidth, JPEG 2000 will adapt optimally. However, this flexibility has a price: the JPEG2000 perplexity is far superior to that of JPEG. This increased complexity can cause problems in applications with real-time constraints. In such cases, the use of a hardware implementation is necessary. In this context, the objective of this paper is the realization of a JPEG2000 encoder architecture satisfying real-time constraints. The proposed architecture will be implemented using programmable chips (FPGA) to ensure its effectiveness in real time. Optimization of renormalization module and byte-out module are described in this paper. Besides, the reduction in computational steps effectively minimizes the time delay and hence the high operating frequency. The design was implemented targeting a Xilinx Virtex 6 and an Altera Stratix FPGAs. Experimental results show that the proposed hardware architecture achieves real-time compression on video sequences on 35 fps at HDTV resolution.

Authors and Affiliations

Taoufik Salem Saidani, Hafedh Mahmoud Zayani

Keywords

Related Articles

Answer Extraction System Based on Latent Dirichlet Allocation

Question Answering (QA) task is still an active area of research in information retrieval. A variety of methods which have been proposed in the literature during the last few decades to solve this task have achieved mixe...

Alerts Clustering for Intrusion Detection Systems: Overview and Machine Learning Perspectives

The tremendous amount of the security alerts due to the high-speed alert generation of high-speed networks make the management of intrusion detection computationally expensive. Evidently, the high-level rate of wrong ale...

Image Blocks Model for Improving Accuracy in Identification Systems of Wood Type

Image-based recognition systems commonly use an extracted image from the target object using texture analysis. However, some of the proposed and implemented recognitionues systems of wood types up to this time have not b...

Improving the Control Strategy of a Standalone PV Pumping System by Fuzzy Logic Technique

This work aims to develop an accurate model of an existing Photovoltaic Pumping System (PvPS) which is composed of an Ebara Pra-0.50T Asynchronous Moto-Pump (AMP) fed by Kaneka GSA-60 photovoltaic panels via a Moeller DV...

Developing a New Hybrid Cipher Algorithm using DNA and RC4

This paper proposes a new hybrid security algorithm called RC4-DNA-Alg. It combines the symmetric stream cipher RC4 algorithm with DNA-indexing algorithm to provide secured data hiding with high complexity inside stegano...

Download PDF file
  • EP ID EP259581
  • DOI 10.14569/IJACSA.2017.080621
  • Views 100
  • Downloads 0

How To Cite

Taoufik Salem Saidani, Hafedh Mahmoud Zayani (2017). Design of a High Speed Architecture of MQ-Coder for JPEG2000 on FPGA. International Journal of Advanced Computer Science & Applications, 8(6), 165-172. https://europub.co.uk/articles/-A-259581