DESIGN OF A HIGH-SPEED WALLACE TREE MULTIPLIER
Journal Title: International Journal of Engineering Sciences & Research Technology - Year 30, Vol 5, Issue 6
Abstract
Multiplication is one of the most common arithmetic operations employed in digital systems, but multipliers are the most time, area, and power consuming circuits. Improvement in any of these parameters can be advantageous for improving the efficiency of the circuit. The ever increasing need for development of efficient and high speed multipliers has motivated several researchers to go a step ahead and present some novel approach. This paper presents an approach towards the reduction of delay in the Wallace tree multipliers by using 4:2 compressors along with fulladders and half-adders, in the partial product reduction stage; and employing Kogge-Stone adder for the final addition. The proposed multiplier has been designed using Xilinx ISE Design Suite 14.7 and implemented for Spartan 3 FPGA.
Authors and Affiliations
Khushboo Bais
Keywords
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- DOI 10.5281/zenodo.55546
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