Design of BER Measurement for MIMO System on FPGA
Journal Title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) - Year 2016, Vol 4, Issue 7
Abstract
The communication systems have become more challenging as difficulty in designing product and cost of product has been increased. In any communication system, bit error rate (BER) plays very important role, if it is high then system performance degrades, so here we are reducing a bit error rate and measure its performance using bit error rate tester (BERT). In this project we are presenting technique called bit error rate performance measurement for MIMO systems to improve performance of data (bit error rate) or data rate of the communication system. In this project we are designing all modules and implemented on the Altera Cyclone IV FPGA.
Authors and Affiliations
G Rashmi, Dr. Baswaraj Gadgay, Suman B Pujari
Keywords
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