Design of Efficient DSP operation using 16×16 R-MAC Unit
Journal Title: International Journal of Research in Computer and Communication Technology - Year 2015, Vol 4, Issue 12
Abstract
As we already know that the multiplication and accumulation are the vital operations involved in DSP `applications. In DSP processor we need high speed performance for different applications. In order to increase this speed of operations implemented the 16x16 R-MAC (Reversible Multiply and Accumulate unit) design. Generally in normal MAC power consumption and heat is somewhat high. This can be reduced by proposed design and also chip life time increases. The normal MAC needs three fetch-decodeexecute cycles to obtain the result. So the circuit has time delay and also high quantum cost. In ReversibleMAC unit need single fetch-decode-execute cycle to obtain the result hence there is no time delay and less quantum cost. The proposed DSP operation using 16x16 R-MAC performs reversible multiplication, addition, accumulation and shifting using peres gate, double peres and Fredkin gates.
Authors and Affiliations
R. Santhi sri, O. Sudha Bharathi
Keywords
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