Design of Energy Efficient Approximate Multiplier
Journal Title: GRD Journal for Engineering - Year 2018, Vol 3, Issue 0
Abstract
Multiplier is one of the arithmetic operations that are used in VLSI circuits. Approximate multiplier is designed by using half adder, full adder and 4-2 compressor. Approximate multiplier is used to reduce the logic gate count, power consumption, delay and it provides high speed output. Area and speed of approximate multiplier is efficient than the conventional multipliers. This adder is mainly used in DSP Application, Image Processing. The simulation result shows the low power consumption by using Xilinx ISE simulation tool.
Authors and Affiliations
J. Gayathri, S. Sowmiya, S. K. Soundriya Leela
Keywords
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