Design of high speed low power Content Addressable Memory (CAM) using parity bit and gated power matchline sensing
Journal Title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) - Year 2015, Vol 3, Issue 3
Abstract
Content Addressable Memory (CAM) offers high speed search function in single clock cycle. Due to its parallel matchline comparison, Content Addressable Memory power is hungry. In general CAM has three operation modes read, write, comparison. The comparison operation to perform n-input search data register into content addressable memory. The recent developments in the design of large capacity of content addressable memory. Thus robust design, high speed and low power Match-Line Sense Amplifiers are highly sought-after in CAM designs. In proposed system are introduced address search in memory location for sensing line, and matchline. A parity bit that reduces to sensing delay reduction. An effective gated power technique to reduce the peak and average power consumption. A feedback loop is employed to auto-turn off the matchline into power supply VDD. The gated power transistor px is controlled by a feedback loop denoted as power control which will automatically turn off once the voltage on the matchline reaches a certain voltage.
Authors and Affiliations
T. Sudalaimani, Mr. S. Muthukrishnan
Keywords
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- EP ID EP19982
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