Design of low offset Dynamic Comparators for High speed ADC Architectures
Journal Title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) - Year 2015, Vol 3, Issue 6
Abstract
A Switched Dynamic Comparator proposed for a 4 bit 12 GS/s ADC solely attains the various requirements under Radio Astronomy. Here the Non-interleaved Full Flash ADC architecture overcomes the mismatches (phase skew error) in traditional Time Interleaved ADC’s using SDC with clock fs/2 followed by reducing the input capacitance. Also, the offset error voltage is cancelled by the Digital Background Calibration circuit.
Authors and Affiliations
Keerthana V, Thiruvalar Selvan P
Keywords
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- EP ID EP20921
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