DESIGN OF LOW POWER HIGH SPEED ERROR TOLERANT ADDERS USING FPGA

Abstract

The addition of two binary numbers is the most fundamental and widely used arithmetic operation. This operation is used in microprocessors, digital signal processors, data processing application specific integrated circuits and many more. ETA (Error Tolerant Adder) is an efficient adder which speeds up binary addition. There is a huge improvement in the power and speed when we use an ETA. For increasing the speed and decreasing the power dissipation, we use the logic that in an adder circuit the delay appears mainly because of the carry propagation and also there is a lot of power dissipation. Design of ETA is done using backend tool under real time simulation conditions and then compares the performance of the ETA in terms of accuracy, delay and power consumption with that of conventional adders. The proposed architecture is then implemented using FPGA.

Authors and Affiliations

LIBYA THOMAS

Keywords

Related Articles

CONSTRUCTING AN INNOVATION ADOPTION CONCEPTUAL LENS/PRELIMINARY FRAME WORK FOR FURTHER TESTING IN UPSTREAM OIL AND GAS

Conceptual Lens helps to focus our study along certain directions for answering the research questions. A Conceptual Lens made from the existing literature helps the researcher to frame relevant questions to be asked t...

POWER-DELAY EFFICIENT ASYNCHRONOUS DESIGN APPROACH USING GALEOR

Leakage power dissipation is a chief alarm in nanometer & deep submicron technologies. In CMOS circuits, leakage current has become major supplier to the whole power dissipation attributable to the unremitting trend of...

CHARGING SYSTEM ANALYSIS IN STATIC AND DYNAMIC WIRELESS ELECTRIC VEHICLE

Depletion in rising fuel prices and green-house gas emissions can be aided by electrified transportation. This evolution urges an installation of diversified charging networks, in an adaptable environment, to be succes...

ZETA CONVERTER SIMULATION FOR CONTINUOUS CURRENT MODE OPERATION

To extract regulated power supply from the inputs of unregulated conditions, the zeta converter topology is the major application in the power electronics current mode operation. Zeta convertor can interfaced for high...

ENHANCEMENT OF ELECTRICAL ENERGY EFFICIENCY BY “INTERNET OF THINGS”

This paper goals at studying the place and possible contribution of “Internet of Things” (IoT) in the context of the EU’s ambitious climate and energy targets for 2020. Using qualitative procedure, we are mainly concen...

Download PDF file
  • EP ID EP46247
  • DOI 10.34218/IJARET.10.1.2019.009
  • Views 286
  • Downloads 0

How To Cite

LIBYA THOMAS (2019). DESIGN OF LOW POWER HIGH SPEED ERROR TOLERANT ADDERS USING FPGA. International Journal of Advanced Research in Engineering and Technology, 10(1), -. https://europub.co.uk/articles/-A-46247