DESIGN OF LOW POWER HIGH SPEED ERROR TOLERANT ADDERS USING FPGA
Journal Title: International Journal of Advanced Research in Engineering and Technology - Year 2019, Vol 10, Issue 1
Abstract
The addition of two binary numbers is the most fundamental and widely used arithmetic operation. This operation is used in microprocessors, digital signal processors, data processing application specific integrated circuits and many more. ETA (Error Tolerant Adder) is an efficient adder which speeds up binary addition. There is a huge improvement in the power and speed when we use an ETA. For increasing the speed and decreasing the power dissipation, we use the logic that in an adder circuit the delay appears mainly because of the carry propagation and also there is a lot of power dissipation. Design of ETA is done using backend tool under real time simulation conditions and then compares the performance of the ETA in terms of accuracy, delay and power consumption with that of conventional adders. The proposed architecture is then implemented using FPGA.
Authors and Affiliations
LIBYA THOMAS
Keywords
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- EP ID EP46247
- DOI 10.34218/IJARET.10.1.2019.009
- Views 284
- Downloads 0
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