Design of Low Power SAR-ADC in 0.18μm Mixed-Mode CMOS Process
Journal Title: International Journal of Research in Computer and Communication Technology - Year 2013, Vol 2, Issue 8
Abstract
This paper presents an energy efficient successive-approximation-register (SAR) analog-todigital converter (ADC) for biomedical applications.For low-power applications designer needs to come up with a compromise among speed, resolution and speed power.To reduce energy consumption, a charge redistribution technique is used along with auto zero technique for comparator offset cancellation.The power consumptions of the capacitive digital-to-analog converter (DAC), latch comparator, and digital control circuit of the proposed ADC are lower than those of a conventional SAR ADC.ADC is designed in 0.18μm CMOS technology in such a way that the total power is minimized while medium sampling rate and 8 bit resolution are achieved.
Authors and Affiliations
RVNR Suneel Krishna, Aleti Shankar
Keywords
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- EP ID EP27637
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