Design of Multioutput High Speed Adder Using Domino Circuit
Journal Title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) - Year 2015, Vol 3, Issue 9
Abstract
Dynamic gates have been excellent choice in the design of high-performance modules such as full adders, subtractors, multipliers, registers, multiplexers and comparators in modern microprocessors. However, the main drawback of dynamic gates is their relatively low noise margin compared to that of standard static logic gates. Traditionally, this problem has been resolved by employing a PMOS keeper transistor in the pull up network that compensates for the sub threshold leakage current of the pull-down NMOS network. In this paper, a new Multioutput ripple carry adder is designed using a technique called current comparison based domino circuit. In this method, a single current mirror circuit is used to track threshold voltage variation in dynamic node. This technique also reduces parasitic capacitance on the dynamic node.
Authors and Affiliations
K. Rajasri, S. Kalpana
Keywords
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