Design of Multiplier and Divider Using Reversible Logic Gates with Vedic Mathematical Approach
Journal Title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) - Year 2014, Vol 2, Issue 9
Abstract
Arithmetic operations are the main components in any design of Digital signal processing or microcontrollers. Multipliers and Divider circuits includes the adders and substations. The main requirements of Digital Signal Processing are High Speed, Low Power and Small Area. To approach these considerations in the designing of Multiplier and Divider Reversibility and Vedic Mathematics approaches are used. The Reversible Logic Gates reduces the Power Dissipation in the Circuit. The Multiplier and Divider are designed by using Reversible logic gates in order to minimize the Power Dissipation of Processors. The Reversible Logic Gates are helps in Quantum Cost Approach. The Speed of the Processor can be improved by reducing the number of multiplications performed per unit time. Hence the system Performance and Efficiency increases. To achieve the requirement the “Urdhva Triyambhayam” concept is introduced. The Urdhva Triyambhayam is taken from the Vedic Mathematics. The proposed Design consists of Multiplier and Divider circuits of Low Power dissipation using Reversible logic gates and High Speed Using Vedic Mathematics. This Design can be applicable in Low Power VLSI and DSP applications, Nano-Technology, Software Defined radios, Cryptography and Wireless Communications. The Design is simulated by using Xilinx 13.2 simulation tool in Verilog Language.
Authors and Affiliations
G. Radhika, D. R. V. A. Sharath Kumar
Keywords
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