Design Of Pipelined RISC MIPS Processor Using VLSI Technology
Journal Title: International Journal of engineering Research and Applications - Year 2018, Vol 8, Issue 9
Abstract
The main aim of this project is to design and implement RISC MIPS processor using VLSI technology. The project involves simulation and synthesis. The processor is designed with Verilog HDL, synthesized using XILINX-13.1. A Reduced Instruction Set compiler (RISC) is a microprocessor that had been designed to perform a small set of instructions, with the aim of increasing the overall speed of the processor. The idea of this project was to create a RISC MIPS processor as a building block in Verilog HDL. Each block is separated by pipeline to speed up the processor. High level of complexity is easier to implement the function in software. The objective of project is to increase the speed and reduce the power consumption. Single cycle execution method applied to complete one instruction through all stages.
Authors and Affiliations
Nyamatulla M Patel, Sachin S Patil, Mamata A Navi, Nilofar B Kanwade
Keywords
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