Design Of Ternary Arithmetic Circuits Using QDGFET
Journal Title: International Journal of Research in Computer and Communication Technology - Year 2015, Vol 4, Issue 4
Abstract
This paper presents a novel design of ternary arithmetic circuits like half-adder and multiplier using quantum dot field effect transistors. Due to the change in threshold voltage over the range QDGFETs produce one intermediate state between two normal stable ON and OFF states. Moreover ternary logic is a promising alternative to the conventional binary logic design technique, since it is possible to produce three states (FALSE, UNKNOWN, TRUE), and also reduces the number of interconnects and chip area and increases efficiency. In this paper we have proposed novel circuit design of half-adder and multiplier based on ternary logic QDGFETs. Increased number of states in QDGFETs will increases the number of bit handling capacity in the device.
Authors and Affiliations
Shah Jay, Prof. Satish Narkhede
Keywords
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- EP ID EP28186
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