Design Optimization of Memristor Based 6T and 7T SRAM Cells using Sleep transistor at Nanoscale Techniques
Journal Title: International Journal of Computational Engineering and Management IJCEM - Year 2016, Vol 19, Issue 2
Abstract
The factors which affect the need of low power design is the rising of leakage current, scaling of technologies and large power dissipation in high performance computing systems. Due to aggressive scaling of devices, leakage current is increasing to an inevitable extent and the efforts have been made to propose an optimized circuit to reduce the power consumption. In this paper, we have proposed a 6T Memristor based SRAM and 7T Memristor based SRAM by employing sleep transistor stacking technique. The outcome has resulted in optimization of leakage current and power dissipation by 16.82% and 45% respectively. At 45 nm technologies, impact of process parameter variations largely affects the proposed circuit. In this paper, the effects and remedies of process parameter variations have also been discussed, explored and elaborated. The results have been validated and compared with the standard results. The simulation results have been carried out in Cadence Virtuoso 45nm technology.
Authors and Affiliations
Vishwas Mishra and Shalini Singh
Keywords
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- EP ID EP195890
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