Designing, simulation and layout of 6bit full adder in cadence software

Journal Title: International Research Journal of Applied and Basic Sciences - Year 2014, Vol 8, Issue 9

Abstract

The bit full adders are highly regarded because of their high application in the electrical circuits. There are several factors that contribute to the superiority of one full adder to another one such as high speed, low energy consumption, less area (fewer transistors), low noise and etc. So, far many adder circuits have been proposed that first to design a full adder; a correct choice should be done between option .In the following, some of the famous full adder circuits are introduced briefly and then the best circuit is selected among them in order to design and draw. The time simulation results of circuit schematic and full adder layout are shown finally .

Authors and Affiliations

Sepideh Fazel| Tabriz Islamic Azad University, email: fazel.sepideh@gmail.com

Keywords

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  • EP ID EP6718
  • DOI -
  • Views 253
  • Downloads 12

How To Cite

Sepideh Fazel (2014). Designing, simulation and layout of 6bit full adder in cadence software. International Research Journal of Applied and Basic Sciences, 8(9), 1283-1288. https://europub.co.uk/articles/-A-6718