Development of Programmable Test Pattern Generator for VLSI Testing
Journal Title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) - Year 2016, Vol 4, Issue 6
Abstract
This paper depicts a low-control (LP) programmable generator equipped for creating pseudorandom test designs with fancied toggling levels and improved fault coverage slope contrasted with the best-to built in self test (BIST)- based pseudorandom test design generators. It is involved a direct limited state machine (A linear feedback shift register or a ring generator) driving a phase shifter, and it accompanies various components permitting this device to deliver binary sequences with preselected toggling (PRESTO) action. We acquaint a strategy with naturally select a few controls of the generator offering simple and exact tuning. The same method is in this way utilized to deterministically direct the generator toward test groupings with enhanced fault coverage . Besides, this paper proposes a LP test pressure strategy that permits modeling the test power envelope in a completely unsurprising, precise, and adaptable style by adjusting the PRESTO-based logic BIST (LBIST) foundation. The proposed half and half plan productively consolidates test pressure with LBIST, where both methods can work synergistically to convey amazing tests.
Authors and Affiliations
Neha Sharma, Dr. Vishal Ramola
Keywords
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