Dynamic Hardware Reconfigurable System Using Partial Reconfiguration Procedure of FPGA

Abstract

Recently, reports about hardware Trojan insertions have been insertions have been on rise. Outsourcing of designs and usage of third party IP cores have put the end user information at stake. It is necessary to have a detailed study to be able to develop organized methods to identify their presence. Many identification methods have been proposed which require a Trojan free chip (Golden Chip). In this paper we introduce about Trojan insertion, methods to detect the Trojan. Reconfigurable systems have been proposed in order to safeguard from Trojan attack. By using the Partial reconfiguration, dynamic modification of the system is analyzed.

Authors and Affiliations

S. Murali, K. Rakesh

Keywords

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  • EP ID EP439115
  • DOI 10.9790/2834-1303016873.
  • Views 148
  • Downloads 0

How To Cite

S. Murali, K. Rakesh (2018). Dynamic Hardware Reconfigurable System Using Partial Reconfiguration Procedure of FPGA. IOSR Journal of Electronics and Communication Engineering(IOSR-JECE), 13(3), 68-73. https://europub.co.uk/articles/-A-439115