Dynamic Power Reduction of Digital Circuits by Clock Gating
Journal Title: International Journal of engineering Research and Applications - Year 2017, Vol 7, Issue 4
Abstract
In this paper we have presented clock gating process for low power VLSI (very large scale integration) circuit design. Clock gating is one of the most quite often used systems in RTL to shrink dynamic power consumption without affecting the performance of the design. One process involves inserting gating requisites in the RTL, which the synthesis tool translates to clock gating cells in the clock-path of a register bank. This helps to diminish the switching activity on the clock network, thereby decreasing dynamic power consumption within the design. Due to the fact the translation accomplished via the synthesis tool is solely combinational; it is referred to as combinational clock gating. This transformation does not alter the behavior of the register being gated.
Authors and Affiliations
Varsha Dewre, Rakesh Mandliya
Keywords
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- EP ID EP391006
- DOI 10.9790/9622-0704050911.
- Views 151
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