Abstract

Clock gating is an effective method of reducing the dynamic power consumption in synchronous circuits. One of the ways to achieve this is by masking the clock that goes to the idle portion of the circuit. In This paper we will present a comparative analysis of existing clock gating techniques on some synchronous digital design like ALU (Arithmetic logical unit) etc. Also a new clock gating technique that provides more immunity to the existing problem in available technique. In new proposed clock gating the Gated Clock Generation Circuit is using tri state buffer and Gated logic is used which is created by the combination of double gated (AND, OR, AND logic gate) with bubbled input respectively. This circuit saves power even when Target device's clock is ON. All experiments are done on Xilinx14.1 EDA tool. Mentor Graphics Model SIM. For power calculation we are using XPOWER. Sparten-3 (90nm) FPGA platform is used for result and analysis. The proposed design will reduce the hardware complexity with approximately 10-20%. Similar clock power complexity will reduce with 5-10%.

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