Effective Approach to Extract CMOS Model Parameters Based On Published Wafer Lot Data
Journal Title: International Journal of engineering Research and Applications - Year 2017, Vol 7, Issue 1
Abstract
The VLSI electronic circuit designs have steadily grown in their capacity and complexity through the years. MOSIS fabrication services provide test data that designers can used to simulat e their circuit designs. The provided test results are extracted from various lot wafers and BSIM3 or BSIM4 model card parameters in addition to technology parameters are provided. It may be cumbersome to ensure design functionality over the wide range of model set of parameters. In this paper, it is proposed to utilize the average model parameters to validate circuit design functionality. It can be shown through device characterization and simple circuit simulations that the average model parameters can provide a good representation of the wide range of supplied model parameters. This is specially attractive for students of circuit design classes where classroom and graduate research work were computing resources are limited. Utilizing average model paramet ers alleviate the need to run simulations over the large set of models from the fabrication facility.
Authors and Affiliations
Ashraf A. Osman, Amin B. Abdel Nabi
Keywords
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- EP ID EP389720
- DOI 10.9790/9622-0701024049.
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