Efficient Architecture for Digital Image Processing Based on EPLD
Journal Title: IOSR Journals (IOSR Journal of Electrical and Electronics Engineering) - Year 2017, Vol 12, Issue 6
Abstract
Digital image processing becomes a wide area of applications that introduce in each part of real life. One of the big challenge of digital image processing is how to speed up the processing speed in order to support the real time application. The main objective of this work is to design a simple method that achieve the digital image processing with in the real time video rate. The architecture of real time digital image processing approach needs high speed components to process a big amount of pixels at minimum time as possible. The implemented approach used Erasable Programmable Logic Device (EPLD) to realize the real time digital image processing. This approach combine both parallel processing and pipeline processing in the architecture. This approach leads to good architecture performance.
Authors and Affiliations
Muzhir Shaban Al-Ani
Keywords
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- EP ID EP388398
- DOI 10.9790/1676-1206010107.
- Views 139
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