Efficient Array Based Approximate Arithmetic Computing Multiplier and Squarer
Journal Title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) - Year 2016, Vol 4, Issue 4
Abstract
Power consumption is one of the most important challenges in arithmetic circuit designs. Exact multiplier produces exact result but it consumes more power which is the main drawback of exact multipliers. The results of approximate multiplier are not exact but the area and power consumption are much less when compared with the exact multipliers. Little accuracy deviation is not an important issue in many applications, hence approximate multiplier is preferred rather than the exact multiplier. The Array based Approximate Arithmetic Computing(AAAC) circuit consists of a Booth multiplier along with the error compensation unit. The Booth multiplier has an adder which combines the outputs of accurate part and the truncated part. An error compensation unit is used to compensate the errors during approximation. The existing approximate and exact multipliers are designed with carry look-ahead adder (CLA) which occupies more area and power requirement is large. This problem is eliminated in efficient AAAC multiplier by carry select adder(CSLA), which helps to improve the performance of the multiplier in terms of area, delay and power. The similar technique is applied to the squarer circuit and significant reduction in area, delay and power are obtained. The Multiplier and Squarer are simulated using Modelsim SE 10.0b software and implemented in Spartan3 FPGA device using Xilinx ISE 9.1i software. Key words—Multiplier, Squarer, Approximate arithmetic computing, Adder.
Authors and Affiliations
E. Pavithra, Dr. B. Sargunam
Keywords
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