Efficient Implementation of 2D- DWT for Video Compression Using Bit Parallel Architecture
Journal Title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) - Year 2015, Vol 3, Issue 6
Abstract
The Discrete wavelet transform (DWT) has gained widespread acceptance in signal processing and image compression. Because of their inherent multi-resolution nature, wavelet-coding schemes are especially suitable for applications where scalability and tolerable degradation are important. Most of the DWT architectures utilize pipelining and combinational logic design to reduce power and chip size. However those designs don’t meet acceptable power. Image memories and intermediate storage are major drawbacks associated with power consumption. By replacing this issue with common memory architecture for both intermediate and default memory storage by using ASIP.
Authors and Affiliations
U. Sowmya
Keywords
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- EP ID EP21012
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