Exploring the self reconfiguration of FPGA: design flow, architecture and performance
Journal Title: International Journal on Computer Science and Engineering - Year 2011, Vol 3, Issue 4
Abstract
Run-time partial reconfiguration of programmable hardware devices can be applied to enhance many applications in high-end embedded systems, particularly those that employ recent platform FPGAs. Partial Reconfigurable FPGAs allow tasks to be placed and removed dynamically at runtime. These reconfigurable systems have a 2-layer hardware and software architecture that permits a variety of different interfaces. Further, these systems enable self-reconfiguration under software control through a reconfiguration hardware interface called Internal Configuration Access Port (ICAP). In this paper, experiments are conducted in order to evaluate the design complexity and reconfiguration latency of self reconfiguration. The results show that the main goal of self reconfiguration is to shorten the reconfiguration time while not degrading the performance of the final design.
Authors and Affiliations
Mohamed Nidhal Krifa , Bouraoui Ouni , Abdellatif Mtibaa
Keywords
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- EP ID EP124317
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