Fair Round Robin: A Low Complexity Packet Scheduler with Proportional and Worst-Case Fairness
Journal Title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) - Year 2016, Vol 4, Issue 3
Abstract
Round robin arbiter (RRA) is a critical block in nowadays designs. It is widely found in System-on-chips and Network-on-chips. The need of an efficient RRA has increased extensively as it is a limiting performance block. In this paper,we deliver a comparative review between different RRA architectures found in literature. We also propose a novel efficient RRA architecture. The FPGA implementation results of the previous RRA architectures and our proposed one are given, that show the improvements of the proposed RRA.
Authors and Affiliations
D. Amsa, K. K. Senthilkumar
Keywords
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- EP ID EP21827
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