FBMC Modulation Scheme Implemented and Simulated in Verilog HDL for 5G Communications
Journal Title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) - Year 2017, Vol 5, Issue 5
Abstract
Filter-Bank Multi-carrier (FBMC) is considered by recent research and projects as a key enabler for future 5g air interface. It helps to eliminate the defect of mobility synchronization and reduce the wastage of resource spectrum bandwidth of currently standardised Orthogonal Frequency Division Multiplexing (OFDM) in 4G communication. Therefore to test the FBMC scheme the availability of an efficient hardware becomes a high interest. Due to software based development facility of hardware unit, the rapid design and testing scenario have originated and applied in rapid scale. So in this paper software based environment Verilog (HDL) Hardware Description Language is used to implement and a virtual simulation is performed to verify the FBMC scheme. The implemented structure can be upgraded to increase the complexity of the hardware structure due to which less hardware resource can be used to design prototype hardware for FBMC scheme.
Authors and Affiliations
Sudeep Kumar Dhurua, T. Venkata Ramana, I. Sreenivasa Rao
Keywords
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