FPGA Based Power Efficient Chanalizer For Software Defined Radio

Journal Title: International Journal of Modern Engineering Research (IJMER) - Year 2014, Vol 4, Issue 2

Abstract

Multiple communication channel support in RF transmission, such as that in a Software Defined Radio (SDR) warrants the use of channelizers to extract required channels from the received RFfrequency band and to perform follow-on baseband processing. This paper describes the process of channelization as it applies to low power and high-efficiency applications in wireless and Satellite Communications (SATCOM) domains. Smaller bandwidths and changing requirements of bandwidth calls for a programmable channel selection mechanism whereby channels and the resulting bandwidth can be selected based on target application, which is the primary principle in the Software Defined Radio based systems.

Authors and Affiliations

Ms. Anuradha S. Deshmukh

Keywords

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  • EP ID EP88185
  • DOI -
  • Views 114
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How To Cite

Ms. Anuradha S. Deshmukh (2014). FPGA Based Power Efficient Chanalizer For Software Defined Radio. International Journal of Modern Engineering Research (IJMER), 4(2), 59-64. https://europub.co.uk/articles/-A-88185