FPGA Design of Pipelined 32-bit Floating Point Multiplier

Abstract

An architecture for a fast 32-bit floating point multiplier compliant with the single precision IEEE 754-2008 standard has been proposed in this paper. Verilog is used to implement a technology-independent pipelined design. Floating Point Multiplier is synthesized and targeted for Xilinx Spartan-3E FPGA.

Authors and Affiliations

Shaifal, Sakshi

Keywords

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  • EP ID EP125724
  • DOI -
  • Views 118
  • Downloads 0

How To Cite

Shaifal, Sakshi (2013). FPGA Design of Pipelined 32-bit Floating Point Multiplier. International Journal of Computational Engineering and Management IJCEM, 16(5), 12-16. https://europub.co.uk/articles/-A-125724