FPGA High Performance Pipelined Architecture Of Elliptic Scalar Multiplication Over GF(2m) for IOT
Journal Title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) - Year 2017, Vol 5, Issue 4
Abstract
The existing era has seen an excellent growth in communications. Various applications like Internet banking, mobile communication, Personal Digital Assistasnce(PDAs), smartcards, etc. have emphasized the need for security in resource constrained environments. Elliptic curve cryptography (ECC) serves as a perfect cryptographic tool as it has short key sizes and security comparable to that of other standard public key algorithms. The efficiency is largely affected by the underlying arithmetic primitives. Multiplication and Inversion are the two most important primitive fields which FPGA design of our concept reveals. The smallest programmable entity in an FPGA is the look up table. The arithmetic algorithms proposed in this thesis maximizes the utilization of LUTs on the FPGA. A novel finite field multiplier based on the recursive Karatsuba algorithm is proposed. The proposed multiplier combines two variants of Karatsuba, The general Karatsuba multiplier has a large gate count but for small sized multiplications is compact because it utilizes LUT resources efficiently. For large sized multiplications, the simple Karatsuba is efficient as it requires lesser gates. In our hybrid multiplier, the simple algorithm performs the initial recursion whereas the general algorithm performs the final multiplication of small sizes. The multiplier thus obtained has the best area time product compared to reported literature.
Authors and Affiliations
Kiran Sulthana S, Dr. V. Ellappan
Keywords
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- EP ID EP23765
- DOI http://doi.org/10.22214/ijraset.2017.4058
- Views 309
- Downloads 7
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