FPGA Implementation of 64-bit fast multiplier using barrel shifter

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FPGA Implementation of 64-bit fast multiplier using barrel shifter

Journal Title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) - Year 2014, Vol 2, Issue 7

Abstract

In this paper we have described the implementation of a 64-bit Vedic multiplier which is enhanced in terms of propagation delay when it is compared with conventional multiplier like modified booth multiplier, Wallace tree multiplier, Braun multiplier, array multiplier. We use various Vedic multiplication techniques for arithmetic operation .It has been found that the most efficient of all the sutra is Urdhva-triyagbhyam, which gives minimum delay for multiplication of all types of numbers, either small or large numbers. For ‘n’ number of shifts only one clock cycle is required in our design, using 64-bit barrel shifter. The design is implemented and verified using ISE simulator and FPGA. Synthesis report and static timing report are used for the comparison of propagation delay. The design uses barrel shifter in base selection module and multiplier which achieves propagation delay of 6.781ns.

Authors and Affiliations

Sweta Khatri, Ghanshyam Jangid

Keywords

EP ID EP18478
DOI -
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