FPGA Implementation of Efficient Viterbi Decoder for Multi-Carrier Systems

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FPGA Implementation of Efficient Viterbi Decoder for Multi-Carrier Systems

Journal Title: International Journal of Modern Engineering Research (IJMER) - Year 2014, Vol 4, Issue 9

Abstract

In this paper, we concern with designing and implementing a Convolutional encoder and Adaptive Viterbi Decoder (AVD) which are the essential blocks in digital communication system using FPGA technology. Convolutional coding is a coding scheme used in communication systems for error correction employed in applications like deep space communications and wireless communications. It provides an alternative approach to block codes for transmission over a noisy channel. The block codes can be applied only for the blocks of data where as the Convolutional coding has an advantage that it can be applied to both continuous data stream and blocks of data. The Viterbi decoder with PNPH (Permutation Network based Path History) management unit which is a special path management unit for faster decoding speed with less routing area. The proposed architecture can be realized by an Adaptive Viterbi Decoder having constraint length, K of 3 and a code rate (k/n) of 1/2 using Verilog HDL. Simulation is done using Xilinx ISE 12.4i design software and it is targeted into Xilinx Virtex-5, XC5VLX110T FPGA

Authors and Affiliations

K. Rajendar , K. Bapayya

Keywords

Convolutional Encoder PNPH Unit Virtex-5 Verilog HDL FPGA. Viterbi decoder Trellis

EP ID EP105371
DOI -
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