FPGA Implementation of Viterbi Decoder for Satellite System
Journal Title: Вісник НТУУ КПІ. Серія Радіотехніка, Радіоапаратобудування - Year 2012, Vol 0, Issue 49
Abstract
Convolutional encoding with Viterbi decoding is a powerful method for forward error correction. This paper presents a short overview of a Viterbi decoder FPGA (Field-Programmable Gate Array) implementation for Thuraya wireless communication sys-tem in Verilog HDL (Hardware Description Language). The main goal of this project was re-source-optimized implementation of the decoder on the target platform. In this project, Viterbi Decoder is implemented on Altera Cyclone III FPGA. The transmitter is of constraint length 5 and of rate 1/4. The Viterbi decoder can operate at a frequency of 90 MHz.
Authors and Affiliations
M. Pavlenko, V. Bychkov
Keywords
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- EP ID EP309182
- DOI 10.20535/RADAP.2012.49.71-76
- Views 77
- Downloads 0
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