FPGA SYNTHESIS AND VALIDATION OF PARALLEL PREFIX ADDERS
Journal Title: Acta Electronica Malaysia (AEM) - Year 2019, Vol 3, Issue 2
Abstract
The main objective of this paper is to attain the best achievable time delay reduction with better performance (i.e. frequency) running on FPGA platforms and prove their applicability in high performance reconfigurable computing in addition to evaluate the FPGA design area and thermal power dispassion. The paper presents description on the implementation of five fast radix-2 parallel prefix adders, namely: Ladner-Fischer Adder (LFA), Brent-Kung Adder (BKA), Kogge-Stone Adder (KSA), Hans-Carlson Adder (HCA), and Sklansky Adder (SkA), with variable data path sizes ranging from 8 bits to 64 bits. The PPA topologies were implemented using VHDL description language and synthesized using Altera Cyclone IV E (EP4CE115 F29C7) FPGA chip device. Intensive tests and verifications were conducted and analyzed validate and evaluate the design cost factors: total path delay time, maximum frequency, design area and the total FPGA thermal power dissipations of the FPGA design as well as the hardware utilization. The results on the code synthesizing demonstrated that the proposed FPGA implementation of KSA has recorded the best values of critical path delay with 4.504 ns for 64 bits while BKA recorded the least design area results with 223 logic elements for the same bit length. In terms of power dissipation, KSA and SkA adders have recorded the best outcomes since they consume the minimum total thermal power dissipation among all other PPAs and for all bit lengths. Thus, the performance of the proposed PPA adders was benchmarked against other state-of-the-art designs which results reflected its superiority in terms of throughput of two or more multiple times as compared to others.
Authors and Affiliations
Qasem Abu Al-Haija, Mohamad Musab Asad, Ibrahim Marouf, Ahmad Bakhuraibah, Hesham Enshasy
Keywords
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- EP ID EP618130
- DOI 10.26480/aem.02.2019.29.34
- Views 73
- Downloads 0
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