Frequency Stability Analysis of 9-stage Ring Oscillator in CMOS 45nm Technology using Cadence Tool

Abstract

This proposed paper focuses on design and analysis of a nine stage Ring Oscillator in terms of frequency stability. For a ring oscillator, accuracy is very important. A 9-stage ring oscillator is designed and simulated using 45nm CMOS process technology. The input control voltage is varied from 0.5V to 1V to examine the frequency stability and power consumption of the circuit. The measured output frequency is 2.384 GHz and output power of 0.223µW. Index Terms: CMOS, Oscillator, frequency stability, Cadence Tool

Authors and Affiliations

N Sandeep, P Sramika Reddy

Keywords

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  • EP ID EP392843
  • DOI 10.9790/9622-0711040710.
  • Views 74
  • Downloads 0

How To Cite

N Sandeep, P Sramika Reddy (2017). Frequency Stability Analysis of 9-stage Ring Oscillator in CMOS 45nm Technology using Cadence Tool. International Journal of engineering Research and Applications, 7(11), 7-10. https://europub.co.uk/articles/-A-392843