Functional Verification of Enhanced RISC Processor
Journal Title: Indian Journal of Computer Science and Engineering - Year 2013, Vol 4, Issue 5
Abstract
This paper presents design and verification of a 32-bit enhanced RISC processor core having floating point computations integrated within the core, has been designed to reduce the cost and complexity. The designed 3 stage pipelined 32-bit RISC processor is based on the ARM7 processor architecture with single precision floating point multiplier, floating point adder/subtractor for floating point operations and 32 x 32 booths multiplier added to the integer core of ARM7. The binary representation of the floating point numbers employed in the design eliminates the need for floating point registers and uses same set of registers thereby reducing the complexity, area and cost. Mask based data reversal barrel shifter performs parallel flag computations during shift or rotate and has least worst case delay of 0.94 ns compared to other barrel shifters. The hardware of the 32-bit RISC processor core has been modeled in Verilog HDL, simulated in VCS. Verification of a complex design such as 32-bit RISC is one of the major challenges as it consumes more time. In this work, a verification environment is being developed to verify the design RISC processor core.
Authors and Affiliations
SHANKER NILANGI , SOWMYA L
Keywords
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