Hardware Co-Simulation of Sobel Edge Detection Using FPGA and System Generator
Journal Title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) - Year 2017, Vol 5, Issue 5
Abstract
This paper implements an image processing algorithm applicable to Edge Detection for still image in a Xilinx FPGA using System Generator. We prefer sobel algorithm which is most reliable and gives us an efficient output. If we prefer to write HDL code for such algorithm in Xilinx FPGA then it’s too bulky and time consuming. We design this system with use of Xilinx System Generator blocks. Its tool with a high- level graphical interface under Matlab environment Its Simulink based blocks which makes it very easy to handle with respect to other software for hardware description. In this paper we have presented new technique SimSH: Simulink Sw/Hw Co Design system. Introduced system gives a programmed way from a algorithm captured in Simulink to a heterogeneous implementation. Given an allotment and a mapping choice, the SimSH automatically synthesizes the Simulink model on heterogeneous target. SimSH also helps to detect underutilized bus and optimize Simulink allows user to concentrate.
Authors and Affiliations
Sneha Moon, Prof Meena Chavan
Keywords
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- EP ID EP24321
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