Hardware Implementation Based on FPGA of AES Encryption and Decryption System
Journal Title: Scholars Journal of Engineering and Technology - Year 2014, Vol 2, Issue 3
Abstract
It is not hard to predict that AES algorithm will play an important role in information security field for a long time in the future after Rijndael algorithm was announced as advanced encryption standard. Hardware implementation based on FPGA of AES algorithm has the advantages of fast, flexible, short development cycle, etc. Hardware implementation based on FPGA of AES encryption and decryption system was studied in this paper concerning the problem that hardware implementation of AES encryption and decryption algorithm on the basis that the overall structure of AES algorithm, basic transformations, encryption and decryption process were all deeply analyzed. First, implementation scheme and key technology to adopt internal and external mixing pipeline structure were determined, and the overall design flow chart was given. Next, considering different application environment, this design supports three modes of encryption and decryption process of AES algorithm under the condition of data group of 128 bits, key length of 128 bits, 192 bits and 256 bits. Therefore, system optimization design of AES encryption and decryption algorithm was completed on the same piece of FPGA chip; Then, coding work and comprehensive compilation was finished by QUARTUS II development tool, and the simulation results by MODELSIM software was given; Finally, this design realized the balance of resources and speed on the basis of guaranteeing speed and had greater advantages in performance. Keywords: AES, FPGA, pipeline, encryption algorithm, decryption algorithm
Authors and Affiliations
Shi-hai Zhu
Keywords
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