Harmonic Minimization in 31-Level Cascaded Multilevel Inverter Topology with Reduced Number of Switches

Abstract

Multilevel inverters are power electronic devices that changes over DC to AC quantity. But these devices produces non-sinusoidal signal which contains harmonics. So as to be overcome this problem a 31-level cascaded multilevel inverter topology was developed. The proposed inverter topology has been designed based on the minimum number of switches, switching power losses and total harmonic distortion[THD] when compared to the symmetrical seven level and asymmetrical fifteen level inverter topology. The simulation results are presented showing the validity of the analysis.

Authors and Affiliations

Koyyana Srinivasa Rao, K. Nagamani, Dhanunjaya Naidu

Keywords

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  • EP ID EP431589
  • DOI 10.9790/1676-1306010713.
  • Views 138
  • Downloads 0

How To Cite

Koyyana Srinivasa Rao, K. Nagamani, Dhanunjaya Naidu (2018). Harmonic Minimization in 31-Level Cascaded Multilevel Inverter Topology with Reduced Number of Switches. IOSR Journals (IOSR Journal of Electrical and Electronics Engineering), 13(6), 7-13. https://europub.co.uk/articles/-A-431589