High Performance of Fault Detection And Correction Technique Using Difference Set Codes For Memory Applications
Journal Title: International Journal of Research in Computer and Communication Technology - Year 2014, Vol 3, Issue 5
Abstract
The advanced combination technologies made it possible for accessing any device so fast that within a portion of seconds the job can be performed. Now days fast memories exists everywhere during accessing if any error happens that has to be detected and corrected within a portion of microseconds that is made potential with help high performance error correcting codes (ECCs) such as LDPC and Turbo Codes.The Majority Logic Decoder (MLD) itself used to detect failures, thus area become minimal and keeps the extra power consumption low. The proposed paper deals with coding and decoding of difference set cyclic codes using majority logic decoding mechanisms. The original control logic is developed for decoding so that error correction can be possible within 3 cycles if the transmitted code vector is error free. The performance result shows that fast error correction prototype is potential with lower area and low power.
Authors and Affiliations
porkodi m, Gopalakrishnan. R
Keywords
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- EP ID EP27924
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