High Speed and Area Efficient Booth Multiplier Using SQRT CSLA with Zero Finding Logic
Journal Title: International Journal of engineering Research and Applications - Year 2017, Vol 7, Issue 4
Abstract
Addition is one of the common and widely used fundamental arithmetic operation in many VLSI systems. The critical elements in general purpose and digital-signal processing processors are High performance VLSI integer adders as they are employed in the design of Arithmetic-Logic Units, in floating-point arithmetic data paths and in address generation units. The performance parameters for any adder are area, speed and delay. By using Square Root Carry Select Adder (SQRT CSLA), speed can be achieved. In designing new architecture, the Tradeoff between those parameters plays the major role. We can reduce area by using Zero Finding Logic (ZFC) technique, from the structure of SQRT CSLA. By using the Modified architecture we can reduce area. We can implement Booth multiplier by using the CSLA and SQRT CSLA with Zero finding logic. Implementation of Booth multiplier by using CSLA and SQRT CSLA with Zero finding logic is proposed for better speed applications and efficient area applications.
Authors and Affiliations
P. Pavani Sushma, J. Priyanka, R. Lalitha, K. Manoj, N. Divya
Keywords
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- EP ID EP390913
- DOI 10.9790/9622-0704017580.
- Views 138
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