High Speed and Resource Efficient Systolic Architecture for Matrix Multiplication using FPGA
Journal Title: GRD Journal for Engineering - Year 2016, Vol 1, Issue 5
Abstract
Grid increase is the piece operation utilized as a part of numerous picture and flag handling applications. This work exhibits a viable configuration for the Matrix Multiplication utilizing Systolic Architecture. This design expands the registering speed by utilizing the idea of parallel handling and pipelining into a solitary idea. The chose stage is a FPGA (Field Programmable Gate Array) gadget since, in systolic registering, FPGAs can be utilized as committed PCs as a part of request to perform certain calculations at high frequencies. The paper exhibits a systolic design for framework duplication calculation utilizing FPGA. Approach utilizes four preparing components that minimizes area, lessens the range and enhances calculation time.
Authors and Affiliations
Anitha PG Scholar, Mr. Pradeep Kumar S K
Keywords
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- EP ID EP218495
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