High Speed Design of an Information Lossless 8 Bit Carry Select Adder using CNT FET
Journal Title: International Journal of Research in Computer and Communication Technology - Year 2013, Vol 2, Issue 3
Abstract
Basic reasons for research on reversible logic are the power consumption and heat dissipation. Existing systems have designed carry select added using TSG gate, for four bit addition. In the proposed system an enhancement of eight bit carry selection is performed with Fault tolerant Full Adder. Cnt fet is used in the implementation of the proposed eight bit carry select adder, which proves the reduction in power is more than 50% than that of existing system.
Authors and Affiliations
S. Manisha Sree Adithtya, S. P. Saraswathi, S. Niranjana
Keywords
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- EP ID EP27551
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